The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for spacers of a field-effect transistor and methods for forming spacers of a field-effect transistor.
Complementary-metal-oxide-semiconductor (CMOS) processes may be used to build a combination of p-channel and n-channel field-effect transistors (nFETs and pFETS) that are coupled to implement logic gates and other types of circuits, such as switches. Field-effect transistors generally include an active semiconductor region, a source, a drain, and a gate electrode. When a control voltage exceeding a threshold voltage is applied to the gate electrode, an inversion or depletion layer is formed in a channel defined in the active semiconductor region between the source and drain by the resultant electric field, and carrier flow occurs between the source and drain to produce a device output current.
The sidewalls of the gate electrode are clad with dielectric spacers to provide electrical isolation. The dielectric spacers may be formed by depositing a conformal layer of a dielectric material and directional dry etching. The dielectric spacers have a minimum thickness that is specified to provide adequate electrical isolation and that takes into account thickness reduction due to erosion as part of a replacement metal gate process. As the gate pitch shrinks with advancements in technology node, the spacing between adjacent gate electrodes for the formation of the dielectric spacers is narrowed. The narrowed spacing may lead to pinch-off when the conformal layer of dielectric material is deposited. Even in the absence of pinch-off, the narrowed spacing may lead to difficulties in filling the space between the spacer-clad gate electrodes with a material used in subsequent patterning of contact openings.